PCIe Schematics

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Published on 19 Jun 2020 - Updated on 05 Dec 2020


  • Add serial capacitor on RX/TX line signal (100nF/0402)
  • Add 50 Ohms pull down resistors on clock line


  • Place serial capacitors as follow

If design uses Connector : Place serial capacitors only on TX line close to the connector
If design uses onboard link : Place serial capacitor near receiver device pin on TX and RX line

  • Place clock pull down resistors as close as possible to clock source (CPU)
  • When using Onboard devices, test points shall be placed near receiver (RX) as follows :

PCI Express testpoint