Ethernet schematics

Schematics

• Check Power pins have the right voltage
• Check for internal power regulators configuration
• Check ethernet PHY I/O voltage levels
• Check crystal frequency, capacitive and resistive load
• Check if reset signal is correctly wired
• Check that PHY is reset at cold and warm boot
• Check RGMII signals are right connected
• Check that MDI signals are right connected
• Check Symbols
• 1x100 nF capacitor per power pin
• Check that terminations are correct
• Check for external required pull up / pull down
• Check that Leds are correctly wired
• Check that interrupts is connected to CPU
• Check that Thermal pad is correctly wired
• Check calibration resistor values
• Check to place an optional ESD device on MDI pins
• Check MDI signals polarity
• Check Serdes signal polarity
• Check how to handle NC pins
• If there is a need for a ferrite bead, make sure there is a bypass capacitor before and after it
• Check that PHYs have different PHY address
• Display configuration table on schematics
• MDC signal shall have a termination resistor near each receiver

• MDIO needs a pull up resistor between 1.5k and 10k
• Oscillators tolerance is +/-50ppm, output jitter is <200ps

Copper

• If PHY does not integrate termination, add 100 Ohms termination resistors to MDI+/-
• Check for unused MDI pins
• Maximum length for MDI pins is 5 inches
• Check for center tap voltage requirement.
• Center tap decoupling capacitor is 100nF
• Check magnetics pinout

RGMII

• TX pins are connected to RX pins
• Unused RX output pins should be left NC
• Unused TX input pins should be pulled low
• If there is no internal impedance calibration, add termination to RXD and RX_CLK pins

SGMII

• 10 nF serial capacitors
• Check polarities

Schematics Checklist